An important factor in the economical manufacture of MOS LSI integrated circuits is reducing the amount of silicon required to produce the semiconductor chips on which the integrated circuits are fabricated. MOS-FET devices and the interconnection pattern of conductors therebetween must be optimized to provide the highest functional component density in order to reduce the chip area per circuit function. Minimum geometry spacings between metallization lines, diffused regions and polycrystalline silicon conductors must be maintained, yet the length of such lines and the associated capacitances must be minimized as complex interconnection patterns are implemented. Parasitic electrical leakage paths in the circuit must be minimized or compensated for in the chip topology. A very high degree of creativity is required of the chip architect in order to choose a particular layout and interconnection pattern for an LSI circuit from the large number of possibilities that exist for arranging such a layout. Frequently, the commercial success of an MOS LSI product may hinge on the ability of the chip architect to achieve an optimumized chip topography.